1. Field of the Invention
The present invention relates to an In Circuit Emulator for a single-chip microcomputer.
2. Related Art
An In Circuit Emulator (hereinafter referred to as an ICE) is one known microcomputer development aiding apparatus. An ICE is a system which incorporates a computer system or a microcomputer which is being developed and cannot develop a software by itself, and is used to debug the software. More specifically, a processor chip of a target computer is detached and a probe of the ICE is attached thereto to emulate operations of a processor or a memory. In other words, in accordance with instructions from the ICE or via a communication line, various functions are performed to develop an arbitrary interruption, the setting of a break point, execution of a single step, display and change of contents of registers and a memory, and execution trace in a system. Such In Circuit Emulator is described in "IE-78600-R In Circuit Emulator hardware manual" published from Nippon Electric Company LTD. in March, 1993, for example.
FIG. 1 is a block diagram showing an emulation board and its periphery which constitute main parts of the driver module block diagram of the ICE disclosed in the above described manual. In FIG. 1, the ICE 300 is connected to a supervisor 351, a main memory 352, and an input and output (I/O) unit 354 through a system bus 353. The ICE 300 may be connected to the supervisor 351 through a communication line. The main memory 352 stores a debug program. The debug program includes functions such as arbitrary interruption of a user program (a program executed by a target device), setting of a break point, execution of a single step, display and change of contents of registers and the memory, and execution trace. The supervisor 351 executes the program stored in the main memory 352, outputs a supervisor interrupt request signal (SVIRQ) 312 to an emulation chip 301, as necessity requires, to instruct the chip 301 what to do.
The ICE 300 comprises an emulation chip 301, an emulation memory 302, an alternate memory 303, an internal bus 304, a composite gate 305, an AND gate 306, an OR gate 307, an inverter 308, and other peripheral circuits (not shown) necessary for performing emulation. The emulation chip 301 comprises a sequencer 309, a flip-flop (F/F) 310 for setting a supervisor flag, a flip-flop (F/F) 322 for setting a macro service request flag 322, and an AND gate 323. The sequencer 309 has an arrangement (a CPU, a ROM, a RAM, and a DMA controller, and the like) and functions similar to that of a target device such as a microcomputer. The sequencer 309 has additional functions such as generation of various control signals necessary for emulation. Specifically, the sequencer 309 generates a SVMOD signal 313, a FETCH signal 314, a SR/W signal 315, a MR/W signal 316, a MSR/W signal 317, a RETSVI signal 320, and a macro service clear signal 322. The SVMOD signal 313 is a signal indicating the supervisor mode, while the FETCH signal 314 indicates fetching of an instruction of a user program stored in an emulation memory 302 (to be described later) in non-supervisor mode (a normal mode), and an instruction of a program stored in an alternate memory 303 in the supervisor mode. The NR/W signal 316 indicates reading/writing of data in the emulation memory 302 in the non-supervisor mode, and reading/writing of data in the alternate memory 303 in the supervisor mode. The SR/W signal 315 is a signal indicating reading/writing from/into the emulation memory 302 in the supervisor mode, while the MSR/W signal 317 is a signal indicating reading/writing from/into the emulation memory 302 when the sequencer 309 is performing a macro service (in the non-supervisor mode). The RETSVI signal 320 is a signal for resetting the supervisor flag (F/F 310), while the macro service clear signal 322 is a signal for resetting a macro service request flag (F/F 311). The AND gate 323 is a gate for blocking the macro service request signal when the SVMOD signal 311 is at logic "1".
The emulation memory 302 stores a user program (a program executed by a target device), and the alternate memory 303 stores a program controlling the emulation chip 301, e.g., a control program for outputting the contents of registers included in the sequencer 309.
The composite gate 305 blocks the FETCH signal 314 and the NR/W signal 316 when the above-described SVMOD signal 313 is active (logic "1"). The AND gate 306 passes the SR/W signal 315 when the SVMOD signal 313 is active (logic "1"), the OR gate 307 receives the output signals of the AND gates 305 and 306 and the MSR/W signal 317, and outputs the chip enable signal to the emulation memory 302 or the alternate memory 303. More specifically, when the output of the OR gate 307 is at logic "1", the active EMEMR/W signal 318 is supplied to the emulation memory 302, and the inactive ALTR/W signal 319, which is inverted by an inverter 308, is supplied to the alternate memory 303. When the output of the OR gate 307 is at logic "0", the active ALTR/W signal 319 is supplied to the alternate memory 303, and the active EMEMR/W signal 319 is supplied to the emulation memory 302.
The sequencer 309 generates the above-described various signals in response to instructions from the supervisor to access the alternate memory 303 or the emulation memory 302, execute the control program stored in the alternate memory 303, output status data in the emulation chip 301 and the contents of various registers, or perform execution trace of the user program stored in the emulation memory 302.
An operation of a conventional in circuit emulator constructed as above will now be described.
First, a reset signal (RESET) from the supervisor 315 is supplied to the emulation chip 301 to reset the same. Then, the supervisor 351 supplies the active SVIRQ signal 312 to the emulation chip 301 to set the supervisor flag. As a result, the SVMOD signal 313 of logic "1" is output from the Q output terminal of the F/F 310 to set the emulation chip 301 in the supervisor mode. Then, the supervisor 351 makes the RESET signal inactive to clear the reset of the emulation chip 301.
The sequencer 309 polls the supervisor flag 310 to determine whether or not an interrupt has been generated by the supervisor 351. If an interrupt has been generated by the supervisor 351, the sequencer 309 executes the supervisor interrupt routine in the alternate memory 303. When the program in the alternate memory 303 is fetched, the sequencer 309 outputs the active (logic "1") FETCH signal 314, with the result that output of the composite gate 305 becomes logic "1". Further, the output of the OR gate 307, --i.e., the EMEMR/W signal 318--becomes logic "0", and the output of the inverter 308, --i.e., the ALTR/W signal 319--becomes logic "1". As a result, the sequencer 309 fetches the instruction in the alternate memory 303.
When the data in the alternate memory 303 is accessed, the sequencer 309 outputs the active (logic "1") NR/W signal 316, with the result that the output of the composite gate 305 becomes logic "0". Further, the output of the OR gate 307--the EMEMR/W signal 318--becomes logic "0", and the output of the inverter 308--i.e., the ALTR/W signal 319--becomes logic "1". As a result, the sequencer 309 reads data from or writes data into the alternate memory 303.
When a special instruction (an emulation memory access instruction) in the control program stored in the alternate memory 303 is executed, the sequencer 309 outputs the active (logic "1") SR/W signal 315, with the result that the output of the AND gate 306 becomes logic "1". Further, the output of the OR gate 307--i.e., the EMEMR/W signal 318--becomes logic "1", and the output of the inverter 308--i.e., the ALTR/W signal 319--becomes logic "0". As a result, the sequencer 309 accesses the emulation memory 302 even in the supervisor mode, in response to the special instruction.
When a macro service request is generated in the supervisor mode, i.e., when the sequencer 309 encounters a macro call instruction during accessing the emulation memory 302 in the supervisor mode, it sets the macro service flag 311. However, since the SVMOD signal 313 is logic "1", the output of the AND gate 323 is logic "0", and therefore the macro service is not executed.
An operation which takes place when the sequencer 309 executes the user program in the emulation memory 302 in the non-supervisor (normal) mode will now be described.
Upon executing a return (RET) instruction in a supervisor interrupt routine, the sequencer 309 outputs the RETSVI signal 320 to reset the supervisor flag 310. As a result, the SVMOD signal 313 becomes logic "0", and the supervisor mode of the emulation chip 301 is cleared.
When the program in the emulation memory 302 is fetched, the sequencer 309 outputs the active (logic "1") FETCH signal. As a result, the output of the composite gate 305 becomes logic "1" and the output of the inverter 308--i.e., the ALTR/W signal 319--becomes logic "0". Accordingly, the sequencer 309 fetches the instruction in the user program in the emulation memory 302.
When data is read from or written into the emulation memory 302, the sequencer 309 outputs the active (logic "1") NR/W signal 316. As a result, the output of the composite gate 305 becomes logic "1". Further, the output of the OR gate--i.e., the EMEMR/W signal 318--becomes logic "1", and the output of the inverter 308--i.e., the ALTR/W signal 319--becomes logic "0". Accordingly, the sequencer 309 reads data from or writes data into the emulation memory 303.
When the macro service request is generated, the sequencer 309 sets the macro service flag to logic "1". As a result, the output of the AND gate 312 becomes logic "1" since the SVMOD signal 313 is logic "0". Therefore, the sequencer 309 executes the macro service. More specifically, the sequencer 309 outputs the active (logic "1") MSR/W signal 317, with the result that the output of the OR gate 307--i.e., the EMEMR/W signal 318--becomes logic "1". Accordingly, the sequencer 309 accesses the macro library stored in the emulation memory 302 to perform a macro development.
Conventionally, in a system comprising a CPU, a DMA controller, and peripheral chips, the DMA controller can be operated even in the supervisor mode by using a memory-I/O demand release mode. However, since in the conventional emulation chip, the supervisor interrupt has the highest priority, execution of the macro service is therefore delayed when the emulation chip is set in the supervisor mode. For this reason, the DMA controller does not operate in the memory-I/O demand release mode, resulting in low-speed processing.